A conventional imaging array comprises an array of pixels, each of which includes a photodetector and the input circuit of a “readout IC” (ROIC) which contains both a capacitor which stores the charge generated by the photodetector in response to light, and electrical circuitry to convey the charge from the photodiode to the capacitor and from the capacitor to further processing circuitry of the ROIC. The ROIC and charge storage capacitors are typically fabricated together using an electronic circuit process, such as CMOS, with the size of each charge storage capacitor limited in part by the size of each pixel and the complexity of the circuit.
Problems may arise when a high-density imaging array is needed. A higher density array requires that the pixel size be small. However, a significant limitation is encountered when attempting to scale to smaller pixel size, in that a smaller pixel necessitates a smaller charge storage capacitor, which serves to reduce the amount of charge that can be stored. This has an adverse effect on the array's sensitivity, typically reflected in the “noise equivalent differential temperature” (NEDT) value, which is a measure of the lowest signal flux level that can be detected by the array. The NEDT value might be lowered by making the charge storage capacitors larger, but this would consume circuit area that might otherwise be used to increase circuit functionality. These factors combine to impede the realization of high performance (low NEDT), high-functionality imaging arrays with small pixel pitch.